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Espressif Systems /ESP32-C6-LP /LP_UART /CONF1

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Interpret as CONF1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RXFIFO_FULL_THRHD 0TXFIFO_EMPTY_THRHD 0 (CTS_INV)CTS_INV 0 (DSR_INV)DSR_INV 0 (RTS_INV)RTS_INV 0 (DTR_INV)DTR_INV 0 (SW_DTR)SW_DTR 0 (CLK_EN)CLK_EN

Description

Configuration register 1

Fields

RXFIFO_FULL_THRHD

It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.
TXFIFO_EMPTY_THRHD

It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.
CTS_INV

Set this bit to inverse the level value of uart cts signal.
DSR_INV

Set this bit to inverse the level value of uart dsr signal.
RTS_INV

Set this bit to inverse the level value of uart rts signal.
DTR_INV

Set this bit to inverse the level value of uart dtr signal.
SW_DTR

This register is used to configure the software dtr signal which is used in software flow control.
CLK_EN

1’h1: Force clock on for register. 1’h0: Support clock only when application writes registers.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data